TT06 sells out. TT07 open!
Sold out - 238 projects submitted from 30 countries.
Tiny Tapeout Team
•20 April 2024
Render of the final submission showing logic density. Analog designs appear almost empty.
We did it!
We sold all the tiles on TT06 - 238 projects submitted from 30 countries.
Across all projects, that’s 9 meters of wire and 267,000 standard cells. The highest utilisation was 93%, achieved by Roland’s Simplez design, and the biggest single project was Luca’s NIST random number generator test with 19,265 cells. Building all the projects took 17 hours.
Verilog was the most popular language with 147 projects, followed by Wokwi with 41 and SystemVerilog with 11. The rest used a mix of other HDLs, including quite a few in Chisel. The datasheet documenting it all runs to 560 pages!
We sold 100% of the Efabless-sponsored PCBs, plus another 60 at full price.
Thanks to Efabless for sponsoring us and making this project possible!
24 analog and mixed-signal designs were submitted, including opamps, ADCs, DACs, and a 555 timer, among others, taking advantage of TT06’s new analog capabilities.
And more than 40 projects came in on the very last day!
Last minute submissions
Thanks to everyone in the Discord who helped new submitters get across the line.
If you missed out on TT06, or want to submit a new version of your design, get involved!
TT07 is now open. Submit your design and join us for the next run!
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Last modified by Matt Venn on 11 July 2026. Commit 2998bd5. Suggestions?