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Tiny Tapeout IHP 0.2
Digital Design Guide
Getting started with our digital design tool
Holidays
Logic Gates
Logic Puzzle - Flip Flop
Logic Puzzle - Edge Detect
Logic Puzzle - Full Adder
Logic Puzzle - Padlock
Customisable Design - Padlock
Customisable Design - UART
Customisable Design - 7-Seg
Simple automated testing using truth tables
Generating Wokwi designs from truth tables
How do semiconductors work?
Introduction to SiliWiz
Draw a Resistor
Parasitics
Voltage Divider
Draw a capacitor
Draw an N MOSFET
Making a logic inverter
Draw a P type MOSFET
Draw a CMOS inverter
Making ASICs
Working with HDLs
Important!
FPGA to ASIC
HDL resources
HDL templates
Testing your design
Competitions
Demoscene
Guides
TT04+ demoboard quickstart
Local hardening
Testing Projects with the Analog Discovery
Workshop
1 - Draw your own MOSFET
Draw and simulate a logic gate with Wokwi
3 - Create the GDS
4 - Submit your design
Tech specs
Clock
GPIO pins
Analog pins
Memory
Pinouts
PCB (TT04+)
PCB (TT02-03)
FAQ
Branding
Contact
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Terms
Credits
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Tiny Tapeout
>
Working with HDLs
> HDL templates
HDL templates
Verilog
https://github.com/TinyTapeout/tt10-verilog-template
This repo shows how to:
specify the files
for building the ASIC
run an automatic test
when you push new code to the repo