359 Simple RISC-V
359 : Simple RISC-V
- Author: kinako71-2
- Description: Simple RISC-V based on the university lecture
- GitHub repository
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- Clock: 0 Hz
How it works
A simple one-stage RISC-V CPU. This CPU was created with reference to the lecture: https://eeic-vlsi.github.io/2025/. Instructions are 32-bit, while the input bus is 8-bit, so each instruction is loaded over four clock cycles.
How to test
Very simple instructions are written in the testbench to verify that the calculations are correct.
External hardware
The chip is not being shipped at this time.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | 1st bit of xth instruction byte | 1st bit of xth alu_out byte | reset to CPU |
| 1 | 2nd bit of xth instruction byte | 2nd bit of xth alu_out byte | write enable to instruction memory |
| 2 | 3rd bit of xth instruction byte | 3rd bit of xth alu_out byte | not used |
| 3 | 4th bit of xth instruction byte | 4th bit of xth alu_out byte | not used |
| 4 | 5th bit of xth instruction byte | 5th bit of xth alu_out byte | not used |
| 5 | 6th bit of xth instruction byte | 6th bit of xth alu_out byte | not used |
| 6 | 7th bit of xth instruction byte | 7th bit of xth alu_out byte | not used |
| 7 | 8th bit of xth instruction byte | 8th bit of xth alu_out byte | not used |