42 ENSEIRB-MATMECA RISC-V processor
42 : ENSEIRB-MATMECA RISC-V processor
- Author: Mathieu Escouteloup
- Description: RISC-V core implementation (32-bit with 8 GPRs)
- GitHub repository
- Open in 3D viewer
- Clock: 50000000 Hz
How it works
It is a simple RISC-V 32-bit implementation.
How to test
There is no implemented test yet.
External hardware
1 input to select boot loader, 1 input for UART Rx, 1 output for Uart Tx, 8 input/outputs for GPIOs
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | BOOT | OUT0_FREE | GPIO0 |
| 1 | IN1_FREE | OUT1_FREE | GPIO1 |
| 2 | IN2_FREE | OUT2_FREE | GPIO2 |
| 3 | UART_RX | OUT3_FREE | GPIO3 |
| 4 | IN4_FREE | UART_TX | GPIO4 |
| 5 | IN5_FREE | OUT5_FREE | GPIO5 |
| 6 | IN6_FREE | OUT6_FREE | GPIO6 |
| 7 | IN7_FREE | OUT7_FREE | GPIO7 |