89 5_1MUX

89 : 5_1MUX

Design renderSelect Project123456789ONSW2
  • Author: saurabh kumar and diksha bothra
  • Description: it's 5 is to 1 mux which trigger only one input and gives output according to the select lines
  • GitHub repository
  • Clock: 0 Hz

How it works

when i give change the logic of clock for diffrent combinations one input is triggered nad at output that input gives output Explain how your project works

How to test

when select i give logic of 000 from S1 ,S2,S3 ,I1 is trigger at 100 I2 is triggered at 001 I3 , 101 I4 and 111 I5 is triggered| Explain how to test your project

IO

#InputOutput
0Clock - S3segment a - OUT0
1I1segment b
2I2segment c
3I3segment d
4I4segment e
5I5segment f
6S1segment g
7S2dot