91 Simple adder used for educational purposes
91 : Simple adder used for educational purposes
- Author: Francisco Brito Filho
- Description: Simple adder used for educational purposes described in VHDL and ported to verilog using ghdl plugin.
- GitHub repository
- Clock: 0 Hz
How it works
The adder was adapted from its 8-bit version. See https://github.com/britovski/adder
How to test
See the testbenchs on the previous github repo.
IO
| # | Input | Output |
|---|---|---|
| 0 | i0[3] | s[3] |
| 1 | i0[2] | s[2] |
| 2 | i0[1] | s[1] |
| 3 | i0[0] | s[0] |
| 4 | i1[3] | co |
| 5 | i1[2] | |
| 6 | i1[1] | |
| 7 | i1[0] |