247 RiscV Scan Chain based CPU -- block 3 -- registers

247 : 0b 011 110 111 : RiscV Scan Chain based CPU – block 3 – registers

Select Project 1 2 3 4 5 6 7 8 9 ON SW2
  • Author: Emilian Miron
  • Description: RiscV Scan Chain based CPU – block 3 – registers
  • GitHub repository
  • HDL project
  • Extra docs
  • Clock: 20000 Hz
  • External hardware:

How it works

TODO

How to test

After reset, the counter should increase by one every second.

IO

# Input Output
0 clock segment a
1 reset segment b
2 none segment c
3 none segment d
4 none segment e
5 none segment f
6 none segment g
7 none slow clock output