It’s a Moore Finite State Machine where the “next step logic” is sinthetized by a Dual-port RAM and latched in a register. “Instructions” are loaded into the ram using port A through a 16 bit shift registed, clocked in A7-A0-D7-D0 format; once loaded they are written into RAM gating the RW pin. The FSM itself uses port B of ram. Two inputs are concatenated with the address, forming the “next state”, and the two ouputs are taken from the Data bus memory. The CLK runs the machine.
# | Input | Output |
---|---|---|
0 | {‘clk_shft’: ‘clock to the 16 bit shift register, risign clock active.’} | {‘salidaQ0’: ‘bit Q0’} |
1 | {‘data_shft’: ‘data to be gated into the 16 bit shift register’} | {‘salidaQ1’: ‘bit Q1’} |
2 | {‘wr_shft’: ‘a pulse here transfers the contents from shift register to RAM’} | {’none’: ‘unused’} |
3 | {‘reset’: ‘active high, resets the 16bit shift reg and the Next State reg’} | {’none’: ‘unused’} |
4 | {‘clk_cpu’: ‘clock to run the FSM’} | {’none’: ‘unused’} |
5 | {’entradaD0’: ‘input bit D0’} | {’none’: ‘unused’} |
6 | {’entradaD1’: ‘input bit D1’} | {’none’: ‘unused’} |
7 | {’none’: ‘unused’} | {’none’: ‘unused’} |