uses a register and some combinational logic
Provides test mode enable to use input clock and inverted ip/clock as emulated encoder CLK/Data
| # | Input | Output |
|---|---|---|
| 0 | clock | segment a |
| 1 | reset_rotary_SW | segment b |
| 2 | rotary_outa | segment c |
| 3 | rotary_outb | segment d |
| 4 | test_mode_enable | segment e |
| 5 | none | segment f |
| 6 | none | segment g |
| 7 | none | none |