63 QTChallenges

I am trying to create a Verilog model for a wrapper around
several benchmarks, sepecifically for the Tiny Tapeout
project. It must meet the following specifications:
    - Inputs:
        - io_in (8-bits)
    - Outputs:
        - io_out (8-bits)

The design should instantiate the following modules, and use
3 bits of the 8-bit input to select which one will output
from the module.

Benchmarks:
    - shift_register:
	    - Inputs:
	    	- clk
	    	- reset_n
	    	- data_in
	    	- shift_enable
	    - Outputs:
	    	- [7:0] data_out

    - sequence_generator:
	    - Inputs:
	    	- clock
	    	- reset_n
	    	- enable
	    - Outputs:
	    	- [7:0] data

    - sequence_detector:
	    - Inputs:
	    	- clk
	    	- reset_n
	    	- [2:0] data
	    - Outputs:
	    	- sequence_found

    - abro_state_machine:
        - Inputs:
            - clk
            - reset_n
            - A
            - B
        - Outputs:
            - O
            - [3:0] state

    - binary_to_bcd:
	    - Inputs:
	    	- [4:0] binary_input
	    - Outputs:
	    	- [3:0] bcd_tens
            - [3:0] bcd_units

    - lfsr:
	    - Inputs:
	    	- clk
            - reset_n
	    - Outputs:
	    	- [7:0] data

    - traffic_light:
        - Inputs:
            - clk
            - reset_n
            - enable
        - Outputs:
            - red
            - yellow
            - green

    - dice_roller:
        - Inputs:
            - clk
            - reset_n
            - [1:0] die_select
            - roll
        - Outputs:
            - rolled_number

How would I write a design that meets these specifications?

I am trying to create a Verilog model for a shift register.
It must meet the following specifications:
	- Inputs:
		- Clock
		- Active-low reset
		- Data (1 bit)
		- Shift enable
	- Outputs:
		- Data (8 bits)

How would I write a design that meets these specifications?

I am trying to create a Verilog model for a sequence
generator. It must meet the following specifications:
	- Inputs:
		- Clock
		- Active-low reset
		- Enable
	- Outputs:
		- Data (8 bits)

While enabled, it should generate an output sequence of the
following hexadecimal values and then repeat:
	- 0xAF
	- 0xBC
	- 0xE2
	- 0x78
	- 0xFF
	- 0xE2
	- 0x0B
	- 0x8D

How would I write a design that meets these specifications?

0xAF
0xBC
0xE2
0x78
0xFF
0xE2
0x0B
0x8D

I am trying to create a Verilog model for a sequence
detector. It must meet the following specifications:
	- Inputs:
		- Clock
		- Active-low reset
		- Data (3 bits)
	- Outputs:
		- Sequence found

While enabled, it should detect the following sequence of
binary input values:
	- 0b001
	- 0b101
	- 0b110
	- 0b000
	- 0b110
	- 0b110
	- 0b011
	- 0b101

How would I write a design that meets these specifications?

0b001
0b101
0b110
0b000
0b110
0b110
0b011
0b101

I am trying to create a Verilog model for an ABRO state
machine. It must meet the following specifications:
    - Inputs:
        - Clock
        - Active-low reset
        - A
        - B
    - Outputs:
        - O
        - State

Other than the main output from ABRO machine, it should
output the current state of the machine for use in
verification.

The states for this state machine should be one-hot encoded.

How would I write a design that meets these specifications?

I am trying to create a Verilog model for a binary to
binary-coded-decimal converter. It must meet the following
specifications:
	- Inputs:
		- Binary input (5-bits)
	- Outputs:
		- BCD (8-bits: 4-bits for the 10's place and 4-bits for the 1's place)

How would I write a design that meets these specifications?

I am trying to create a Verilog model for an LFSR. It must
meet the following specifications:
	- Inputs:
		- Clock
        - Active-low reset
	- Outputs:
		- Data (8-bits)

The initial state should be 10001010, and the taps should be
at locations 1, 4, 6, and 7.

How would I write a design that meets these specifications?

I am trying to create a Verilog model for a traffic light
state machine. It must meet the following specifications:
    - Inputs:
        - Clock
        - Active-low reset
        - Enable
    - Outputs:
        - Red
        - Yellow
        - Green

The state machine should reset to a red light, change from
red to green after 32 clock cycles, change from green to
yellow after 20 clock cycles, and then change from yellow to
red after 7 clock cycles.

How would I write a design that meets these specifications?

I am trying to create a Verilog model for a simulated dice
roller. It must meet the following specifications:
    - Inputs:
        - Clock
        - Active-low reset
        - Die select (2-bits)
        - Roll
    - Outputs:
        - Rolled number (up to 8-bits)

The design should simulate rolling either a 4-sided,
6-sided, 8-sided, or 20-sided die, based on the input die
select. It should roll when the roll input goes high and
output the random number based on the number of sides of the
selected die.

How would I write a design that meets these specifications?

Can you create a Verilog testbench for this design? It
should be self-checking and made to work with iverilog for
simulation and validation. If test cases should fail, the
testbench should provide enough information that the error
can be found and resolved.