Uses a set of registers to divide the clock, and then some combinational logic to convert from binary to decimal for the display.
Puts a slower square wave output on output 7.
After reset, the counter should increase by one every second.
| # | Input | Output |
|---|---|---|
| 0 | clock | segment a |
| 1 | reset | segment b |
| 2 | none | segment c |
| 3 | none | segment d |
| 4 | none | segment e |
| 5 | none | segment f |
| 6 | none | segment g |
| 7 | none | slow clock output |