128 serv - Serial RISCV CPU

128 : serv - Serial RISCV CPU

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  • Author: Greg Davill
  • Description: An award winning RISCV CPU!
  • GitHub repository
  • Clock: 0 Hz

How it works

This project contains a 96bit serial scanchain, and the core of the serv CPU. Signals present on the scanchain are a wishobne bus and the native registerfile interface. As there is not enough room inside the TinyTapeout project area to fit RAM/registerfiles these have to be implemented externally. In theory just a bit of custom code running on caravel will be enough to get the serv core running.

How to test

tbd

External hardware

tbd

Picture

IO

#InputOutput
0clocksegment a
1resetsegment b
2segment c
3segment d
4segment e
5segment f
6segment g
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