165 MRCS Verilog test
165 : MRCS Verilog test
- Author: Steven Bos
- Description: Testing various auto-generated verilog for various sync and async logic gates
- GitHub repository
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How it works
This Project contains various latches and one edge detector.
A larger description will follow.
How to test
A complete description to test will follow.
There are 5 components to test.
External hardware
none
IO
| # | Input | Output |
|---|---|---|
| 0 | clock | |
| 1 | ||
| 2 | ||
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| 7 |