165 MRCS Verilog test

165 : MRCS Verilog test

Select Project123456789ONSW2
  • Author: Steven Bos
  • Description: Testing various auto-generated verilog for various sync and async logic gates
  • GitHub repository
  • Clock: 0 Hz

How it works

This Project contains various latches and one edge detector.

A larger description will follow.

How to test

A complete description to test will follow.

There are 5 components to test.

External hardware

none

IO

#InputOutput
0clock
1
2
3
4
5
6
7