132 MicroASIC VI

132 : MicroASIC VI

Design renderSelect Project123456789ONSW2
  • Author: Mikhail Svarichevsky
  • Description: Free-running oscillators to verify simulation vs reality + TRNG
  • GitHub repository
  • Clock: 1000 Hz

How it works

Combinational loops with dividers to bring output frequency to <50kHz range

How to test

Select oscillator (pins 4-6) and mesaure frequency on one of output pins. Observe true random numbers at pin 7.

External hardware

You might benefit from frequency counter than can do averaging across extended period of time.

IO

#InputOutput
0clock in (for debugging)clock divided by 2^10
1resetclock divided by 2^14
2shift register clkclock divided by 2^18
3shift register dataclock divided by 2^22
4clock source id_0clock divided by 2^26
5clock source id_1clock divided by 2^30
6clock source id_2clock divided by 2^32
7Bit 11 of shift register (to ensure it's not optimized away)