128 serv - Serial RISCV CPU

128 : serv - Serial RISCV CPU

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How it works

This project contains a 96bit serial scanchain, and the core of the serv CPU. Signals present on the scanchain are a wishobne bus and the native registerfile interface. As there is not enough room inside the TinyTapeout project area to fit RAM/registerfiles these have to be implemented externally. In theory just a bit of custom code running on caravel will be enough to get the serv core running.

How to test



# Input Output
0 clock segment a
1 reset segment b
2 none segment c
3 none segment d
4 none segment e
5 none segment f
6 none segment g
7 none none