See the full documentation, youtube movie and image. Each 1-bit counter has a flip-flop with count logic component reacting synchronously to the rising edge clock pulse and a count logic component that computes and setup the behavior for the next rising edge using async propagation when the level is low.
The count state is randomly initialized. Typically the first action is to reset the state to zero by setting the load switch and have one clock pulse. The second action is setting the direction by enabling count and setting countDown to true or false (and disable load). The counter overflows to all 0 when all 1 is reached and count up is set.
|0||clock||output3 (bits [0:3])|
|1||count (0 = disable/countPause, 1 = enable)||output2|
|2||load (0 = count mode, 1 = load mode, overwriting any count logic)||output1|
|3||countDown (0 = countUp, 1 = countUp)||output0|
|4||addr3 (bits[4:7] are used for loadable count state)||none|