After ena=1 and the reset cycle, a counter counts the number of cycles of the selected ring oscillator in one period of the system clock. the ring oscillator is selected by osc_sel input, each oscillator have different frequency.
This count is added cumulatively, the number of counts added is given by the entry sum_sel: (sum_sel+1)*4 = number of counts added.
When the data 0x00 (START CODE) is received by the uart, the sum total of three bytes long is sent back in LSB first.
additionally, on each clock cycle the output of the oscillator cycle counter is divided by 2 and sent to the output uo_out[7:1] and uio_out[7:0].
After reset and enable are set, the ring oscillator should start and then when a START code (0x00) is received by UART, the cumulative sum value of 3 bytes is sent back. The oscillator counter divided by 2 is present on uo_out[7:1] and uio_out[7:0].
|0||ui_in = clk_external||uo_out = tx (UART tx)||[‘uio_out[7:0] = oscillator counter bits 15 to 8’]|
|1||ui_in = clk_sel (select the system clock input)||uo_out[7:1] = oscillator counter bits 7 to 1||n/a|
|2||ui_in[4:2] = sum_sel (number of oscillator counts added (sum_sel+1)*4)||n/a||n/a|
|3||ui_in = rx (UART RX)||n/a||n/a|
|4||ui_in[7:6] = osc_sel (select one of 4 ring oscillators)||n/a||n/a|