Its a 4-bit ring-shift register with a single ‘1’ cycling through it after reset.
After starting the clock, the 4 outputs will remain off or in a random state until the reset input is activated. Then it should work as described.
# | Input | Output |
---|---|---|
0 | CLK | O_0 |
1 | RST | O_1 |
2 | none | O_2 |
3 | none | O_3 |
4 | none | none |
5 | none | none |
6 | none | none |
7 | none | none |