Segments of the 7seg display are activated in a sequence controlled by a finite state machine. The state is represented by 14 flipflops. Each segment has two flipflops, one for each direction of the walk. Where a segment has two possible successors, a mux selects between them, controlled by the output from a linear feedback shift register acting as a random number generator. The FSM is self initialising so a reset signal isn’t required: the number of true flipfops is summed, and if the total isn’t exactly 1 the state will be initialised to have a single segment and direction active. A clock divider is used to slow the walk to a visible speed. This is done by gating the flipflop state transitions with a pulse generated every 2^N clock cycles (where N is a 4-bit number set by the DIP switches.) The pulses are obtained by using a tree of muxes controlled by the bits of N to select one carry bit from within a 16-bit counting register.
Use switches 5-8 (LSB is switch 8) to set a number N from 0 to 15; the clock will be divided by 2^N. To test the clock, set switch 4 on and the 7seg dot will flash at half the clock speed.
|3||enable flashing dot||segment d|
|4||clock divisor bit 3 (MSB)||segment e|
|5||clock divisor bit 2||segment f|
|6||clock divisor bit 1||segment g|
|7||clock divisor bit 0 (LSB)||dot|