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Tiny Tapeout 03
> 17 TinyFPGA attempt for TinyTapeout3
17 : TinyFPGA attempt for TinyTapeout3
17 TinyFPGA attempt for TinyTapeout3
17 : TinyFPGA attempt for TinyTapeout3
Author: Emilian Miron
Description: FPGA attempt
GitHub repository
Most recent GDS build
HDL project
Extra docs
Clock: 1000 Hz
External hardware:
How it works
TODO
How to test
After reset, the counter should increase by one every second.
IO
#
Input
Output
0
clock
segment a
1
reset
segment b
2
none
segment c
3
none
segment d
4
none
segment e
5
none
segment f
6
none
segment g
7
none
slow clock output