16 bad apple

16 : 0b 000 010 000 : bad apple

Select Project 1 2 3 4 5 6 7 8 9 ON SW2

How it works

Converts an RTTL ringtone into verilog and plays it back using differential PWM modulation.

How to test

Provide 12kHz clock on io_in[0], briefly hit reset io_in[1] (L->H->L) and io_out[1:0] will play a differential sound wave over piezo speaker (Bad Apple)

IO

# Input Output
0 clock piezo_speaker_p
1 reset piezo_speaker_n
2 none none
3 none none
4 none none
5 none none
6 none none
7 none none